HPC Platform Selects Altera Stratix II FPGA Family for New HMPE System

HPC Platform of Paris, France, has selected two members of the Altera Corporation's Stratix II FPGA family for use in their ultra-low latency system for market data processing, algorithmic trading and complex financial product valuation acceleration. The Hardware Messaging and Processing Engine (HMPE) features an optimized modular architecture, domain specific language (DSL) compilers and software environments that enable customers to effectively use FPGAs as reconfigurable hardware.

The HPC Platform HPME is based on a PCI Express (PCIe) board with a Stratix II GX FPGA that interfaces to several other boards with embedded QDRII memory and a Stratix II FPGA for acceleration (algorithmic processing). These boards are interfaced via 144 x 1-Gbps LVDS channels. With up to eight integrated transceiver channels and support for high-speed, low-latency memory access via a QDRII memory interface, the development board provides a fully integrated solution for multi-channel, high-performance applications, while also using limited board space. Targeting key applications in the financial marketplace, the HPME looks for low-latency including feed handling and complex event processing (CEP) for algorithmic trading strategies, as well as Monte Carlo options and derivatives pricing and risk computations. Using full hardware processing, the HPME achieves performance with a latency of 1.1 to 2.0 microseconds in market data processing, including orders book management.

"We have worked closely with Altera and leading investment banks to demonstrate ultra-low-latency feed handling and complex derivatives valuation acceleration as well as low-latency triggering of algorithmic trading CEP events," said Marc Battyani, co-founder of HPC Platform, in a press release. "Our appliances demonstrate the lowest latency available today. Traditional solutions can not efficiently address the ever-increasing growth in the complexity and volume of financial products," he added.